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ltc1196/ltc1198 1 119698fb typical application features applications description 8-bit, so-8, 1msps adcs with auto-shutdown options single 5v supply, 1msps, 8-bit sampling adc n high speed data acquisition n disk drives n portable or compact instrumentation n low power or battery-operated systems n high sampling rates: 1mhz (ltc1196) 750khz (ltc1198) n low cost n single supply 3v and 5v speci? cations n low power: 10mw at 3v supply 50mw at 5v supply n auto-shutdown: 1na typical (ltc1198) n 1/2lsb total unadjusted error over temperature n 3-wire serial i/o n 1v to 5v input span range (ltc1196) n converts 1mhz inputs to 7 effective bits n differential inputs (ltc1196) n 2-channel mux (ltc1198) n so-8 plastic package the ltc ? 1196/ltc1198 are 600ns, 8-bit a/d converters with sampling rates up to 1mhz. they are offered in 8-pin so packages and operate on 3v to 6v supplies. power dissipation is only 10mw with a 3v supply or 50mw with a 5v supply. the ltc1198 automatically powers down to a typical supply current of 1na whenever it is not performing conversions. these 8-bit switched-capacitor successive approximation adcs include sample-and- holds. the ltc1196 has a differential analog input; the ltc1198 offers a software selectable 2-channel mux. the 3-wire serial i/o, so-8 packages, 3v operation and extremely high sample rate-to-power ratio make these adcs an ideal choice for compact, high speed systems. these adcs can be used in ratiometric applications or with external references. the high impedance analog in- puts and the ability to operate with reduced spans below 1v full scale (ltc1196) allow direct connection to signal sources in many applications, eliminating the need for gain stages. the a-grade devices are speci? ed with total unadjusted error of 1/2lsb maximum over temperature. effective bits and s/(n + d) vs input frequency input frequency (hz) 1k s/(n + d) (db) 8 7 6 5 4 3 2 1 0 10k 100k 1m 11968 ta01b 50 44 effective number of bits (enobs) v ref =v cc = 2.7v f smpl = 383khz (ltc1196) f smpl = 287khz (ltc1198) v ref =v cc = 5v f smpl = 1mhz (ltc1196) f smpl = 750khz (ltc1198) t a = 25c 5v 1f analog input 0v to 5v range 1196/98 ta01 serial data link to asic, pld, mpu, dsp, or shift registers Cin gnd v cc clk d out +in cs 1 2 3 4 8 7 6 5 ltc1196 v ref l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc1196/ltc1198 2 119698fb absolute maximum ratings (notes 1, 2) 1 2 3 4 8 7 6 5 top view v cc clk d out v ref s8 package 8-lead plastic so cs +in Cin gnd t jmax = 150c, ja = 175c/w 1 2 3 4 8 7 6 5 top view v cc (v ref ) clk d out d in ch0 ch1 gnd s8 package 8-lead plastic so cs / shutdown t jmax = 150c, ja = 175c/w pin configuration order information lead free finish tape and reel part marking package description temperature range ltc1196-1acs8#pbf ltc1196-1acs8#trpbf 11961a 8-lead plastic so 0c to 70c ltc1196-1bcs8#pbf ltc1196-1bcs8#trpbf 11961b 8-lead plastic so 0c to 70c ltc1196-2acs8#pbf ltc1196-2acs8#trpbf 11962a 8-lead plastic so 0c to 70c ltc1196-2bcs8#pbf ltc1196-2bcs8#trpbf 11962b 8-lead plastic so 0c to 70c ltc1198-1acs8#pbf ltc1198-1acs8#trpbf 11981a 8-lead plastic so 0c to 70c ltc1198-1bcs8#pbf ltc1198-1bcs8#trpbf 11981b 8-lead plastic so 0c to 70c ltc1198-2acs8#pbf ltc1198-2acs8#trpbf 11982a 8-lead plastic so 0c to 70c ltc1198-2bcs8#pbf ltc1198-2bcs8#trpbf 11982b 8-lead plastic so 0c to 70c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ supply voltage (v cc ) to gnd .................................... 7v voltage analog reference ....................... C0.3v to v cc + 0.3v digital inputs ......................................... C0.3v to 7v digital outputs ........................... C0.3v to v cc + 0.3v power dissipation .............................................. 500mw operating temperature range ltc1196-1ac, ltc1198-1ac, ltc1196-1bc, ltc1198-1bc, ltc1196-2ac, ltc1198-2ac, ltc1196-2bc, ltc1198-2bc ................. 0c to 70c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................ 300c ltc1196 ltc1198
ltc1196/ltc1198 3 119698fb recommended operating conditions symbol parameter conditions min ltc1196-1 ltc1198-1 typ max min ltc1196-2 ltc1198-2 typ max units v cc supply voltage 2.7 6 2.7 6 v v cc = 5v operation f clk clock frequency l 0.01 0.01 14.4 12.0 0.01 0.01 12.0 9.6 mhz mhz t cyc total cycle time ltc1196 ltc1198 12 16 12 16 clk clk t smpl analog input sampling time 2.5 2.5 clk t h cs hold time cs low after last clk 10 13 ns t su cs setup time cs before first clk (see figures 1, 2) 20 26 ns t hdi hold time d in after clk ltc1198 20 26 ns t sudi setup time d in stable before clk ltc1198 20 26 ns t whclk clk high time f clk = f clk(max) 40% 40% 1/f clk t wlclk clk low time f clk = f clk(max) 40% 40% 1/f clk t wh cs cs high time between data transfer cycles 25 32 ns t wl cs cs low time during data transfer ltc1196 ltc1198 11 15 11 15 clk clk the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. converter and multiplexer characteristics parameter conditions ltc1196-1a/ltc1196-2a ltc1198-1a/ltc1198-2a ltc1196-1b/ltc1196-2b ltc1198-1b/ltc1198-2b units min typ max min typ max no missing codes resolution l 8 8 bits offset error l 1/2 1 lsb linearity error (note 3) l 1/2 1 lsb full-scale error l 1/2 1 lsb total unadjusted error (note 4) ltc1196, v ref = 5.000v ltc1198, v cc = 5.000v l 1/2 1 lsb analog and ref input range ltc1196 C0.05v to v cc + 0.05v v analog input leakage current (note 5) l 1 1 a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v ref = 5v, f clk = f clk(max) as de? ned in recommended operating conditions, unless otherwise noted. digital and dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v ref = 5v, unless otherwise noted. symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 a i il low level input current v in = 0v l C2.5 a v oh high level output voltage v cc = 4.75v, i o = 10a v cc = 4.75v, i o = 360a l l 4.5 2.4 4.74 4.71 v v
ltc1196/ltc1198 4 119698fb digital and dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v ref = 5v, unless otherwise noted. symbol parameter conditions min typ max units v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz hi-z output leakage cs = high l 3 a i source output source current v out = 0v C25 ma i sink output sink current v out = v cc 45 ma i ref reference current, ltc1196 cs = v cc f smpl = f smpl(max) l l 0.001 0.5 3 1 a ma i cc supply current cs = v cc , ltc1198 (shutdown) cs = v cc , ltc1196 f smpl = f smpl(max) , ltc1196/ltc1198 l l l 0.001 7 11 3 15 20 a ma ma dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v ref = 5v, f clk = f clk(max) as de? ned in recommended operating conditions, unless otherwise noted. symbol parameter conditions min ltc1196 typ max min ltc1198 typ max units s/(n + d) signal-to-noise plus distortion 500khz/1mhz input signal 47/45 47/45 db thd total harmonic distortion 500khz/1mhz input signal 49/47 49/47 db peak harmonic or spurious noise 500khz/1mhz input signal 55/48 55/48 db imd intermodulation distortion f in1 = 499.37khz f in2 = 502.446khz 51 51 db full-power bandwidth 8 8 mhz full linear bandwidth [s/(n + d) > 44db 1 1 mhz ac characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v, v ref = 5v, f clk = f clk(max) as de? ned in recommended operating conditions, unless otherwise noted. symbol parameter conditions min ltc1196-1 ltc1198-1 typ max min ltc1196-2 ltc1198-2 typ max units t conv conversion time (see figures 1, 2) l 600 710 710 900 ns ns f smpl(max) maximum sampling frequency ltc1196 ltc1196 ltc1198 ltc1198 l l 1.20 1.00 0.90 0.75 1.00 0.80 0.75 0.60 mhz mhz mhz mhz t ddo delay time, clk to d out data valid c load = 20pf l 55 64 73 68 78 94 ns ns t dis delay time cs to d out hi-z l 70 120 88 150 ns t en delay time, clk to d out enabled c load = 20pf l 30 50 43 63 ns t hdo time output data remains valid after clk c load = 20pf l 30 45 30 55 ns t f d out fall time c load = 20pf l 515 1020ns t r d out rise c load = 20pf l 515 1020ns c in input capacitance analog input on channel analog input off channel digital input 30 5 5 30 5 5 pf pf pf
ltc1196/ltc1198 5 119698fb recommended operating conditions the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v operation. symbol parameter conditions min ltc1196-1 ltc1198-1 typ max min ltc1196-2 ltc1198-2 typ max units f clk clock frequency l 0.01 0.01 5.4 4.6 0.01 0.01 4 3 mhz mhz t cyc total cycle time ltc1196 ltc1198 12 16 12 16 clk clk t smpl analog input sampling time 2.5 2.5 clk t h cs hold time cs low after last clk 20 40 ns t su cs setup time cs before first clk (see figures 1, 2) 40 78 ns t hdi hold time d in after clk ltc1198 40 78 ns t sudi setup time d in stable before clk ltc1198 40 78 ns t whclk clk high time f clk = f clk(max) 40% 40% 1/f clk t wlclk clk low time f clk = f clk(max) 40% 40% 1/f clk t wh cs cs high time between data transfer cycles 50 96 ns t wl cs cs low time during data transfer ltc1196 ltc1198 11 15 11 15 clk clk converter and multiplexer characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as de? ned in recommended operating conditions, unless otherwise noted. digital and dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v, v ref = 2.5v, unless otherwise noted. symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 1.9 v v il low level input voltage v cc = 2.7v l 0.45 v i ih high level input current v in = v cc l 2.5 a i il low level input current v in = 0v l C2.5 a v oh high level output voltage v cc = 2.7v, i o = 10a v cc = 2.7v, i o = 360a l l 2.3 2.1 2.60 2.45 v v v ol low level output voltage v cc = 2.7v, i o = 400a l 0.3 v i oz hi-z output leakage cs = high l 3 a parameter conditions ltc1196-1a/ltc1196-2a ltc1198-1a/ltc1198-2a ltc1196-1b/ltc1196-2b ltc1198-1b/ltc1198-2b units min typ max min typ max no missing codes resolution l 8 8 bits offset error l 1/2 1 lsb linearity error (note 3) l 1/2 1 lsb full-scale error l 1/2 1 lsb total unadjusted error (note 4) ltc1196, v ref = 2.5.000v ltc1198, v cc = 2.700v l 1/2 1 lsb analog and ref input range ltc1196 C0.05v to v cc + 0.05v v analog input leakage current (note 5) l 1 1 a
ltc1196/ltc1198 6 119698fb digital and dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v, v ref = 2.5v, unless otherwise noted. symbol parameter conditions min typ max units i source output source current v out = 0v C10 ma i sink output sink current v out = v cc 15 ma i ref reference current, ltc1196 cs = v cc f smpl = f smpl(max) l l 0.001 0.25 3.0 0.5 a ma i cc supply current cs = v cc = 3.3v, ltc1198 (shutdown) cs = v cc = 3.3v, ltc1196 f smpl = f smpl(max) , ltc1196/ltc1198 l l l 0.001 1.5 2.0 3.0 4.5 6.0 a ma ma dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as de? ned in recommended operating conditions, unless otherwise noted. symbol parameter conditions min ltc1196 typ max min ltc1198 typ max units s/(n + d) signal-to-noise plus distortion 190khz/380khz input signal 47/45 47/45 db thd total harmonic distortion 190khz/380khz input signal 49/47 49/47 db peak harmonic or spurious noise 190khz/380khz input signal 53/46 53/46 db imd intermodulation distortion f in1 = 189.37khz f in2 = 192.446khz 51 51 db full-power bandwidth 5 5 mhz full linear bandwidth [s/(n + d) > 44db 0.5 0.5 mhz ac characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as de? ned in recommended operating conditions, unless otherwise noted. symbol parameter conditions min ltc1196-1 ltc1198-1 typ max min ltc1196-2 ltc1198-2 typ max units t conv conversion time (see figures 1, 2) l 1.58 1.85 2.13 2.84 s s f smpl(max) maximum sampling frequency ltc1196 ltc1196 ltc1198 ltc1198 l l 450 383 337 287 333 250 250 187 khz khz khz khz t ddo delay time, clk to d out data valid c load = 20pf l 100 150 180 130 200 250 ns ns t dis delay time cs to d out hi-z l 110 220 120 250 ns t en delay time, clk to d out enabled c load = 20pf l 80 130 100 200 ns t hdo time output data remains valid after clk c load = 20pf l 45 90 45 120 ns t f d out fall time c load = 20pf l 10 30 15 40 ns t r d out rise c load = 20pf l 10 30 15 40 ns c in input capacitance analog input on channel analog input off channel digital input 30 5 5 30 5 5 pf pf pf note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime.
ltc1196/ltc1198 7 119698fb frequency (mhz) 0 supply current (ma) 12 9 8 7 6 5 4 3 2 1 0 1196/98 g01 216 468 10 14 t a = 25c cs = 0v v ref = v cc v cc = 5v v cc = 2.7v supply voltage (v) 2.5 14 12 10 8 6 4 2 0 4.0 5.0 1196/98 g02 3.0 3.5 4.5 5.5 6.0 supply current (ma) t a = 25c 0.000002 ltc1196 ltc1198 active mode cs = 0v shutdown mode cs = v cc ltc1198 sample rate (hz) 0.01 supply current (ma) 0.1 1 10 100 10k 100k 1196/98 g03 0.001 1k 1m lt1196 v cc = 5v lt1196 v cc = 2.7v lt1198 v cc = 5v lt1198 v cc = 2.7v t a = 25c temperature (c) C55 supply current (ma) 10 9 8 7 6 5 4 3 2 1 0 C15 25 45 125 1196/98 g04 C35 5 65 85 105 cs = 0v v cc = 5v v cc = 2.7v reference voltage (v) 0.5 magnitude of offset (lsb = s v ref ) 5.0 1196/98 g05 3.5 2.5 4.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.0 2.0 1.5 4.5 3.0 t a = 25c v cc = 5v f clk = 12mhz 1 256 supply voltage (v) 2.5 magnitude of offset (lsb) 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 3.5 4.5 5.0 1196/98 g06 3.0 4.0 5.5 6.0 t a = 25c v ref = v cc f clk = 3mhz note 2: all voltage values are with respect to gnd. note 3: integral nonlinearity is de? ned as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 4: total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. note 5: channel leakage current is measured after the channel selection. electrical characteristics typical performance characteristics supply current vs clock rate supply current vs supply voltage supply current vs sample rate supply current vs temperature offset vs reference voltage offset vs supply voltage
ltc1196/ltc1198 8 119698fb typical performance characteristics linearity error vs reference voltage linearity error vs supply voltage supply current vs sample rate minimum clock rate for 0.1lsb* error adc noise vs referenced and supply voltage sample-and-hold acquisition time vs source resistance gain vs supply voltage maximum clock frequency vs supply voltage maximum clock frequency vs source resistance reference voltage (v) linearity error (lsb) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1196/98 g07 0.5 5.0 3.5 2.5 4.0 1.0 2.0 1.5 4.5 3.0 t a = 25c v cc = 5v f clk = 12mhz supply voltage (v) 2.5 linearity error (lsb) 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 3.5 4.5 5.0 1196/98 g08 3.0 4.0 5.5 6.0 t a = 25c v ref = v cc f clk = 3mhz reference voltage (v) 0 magnitude of gain error (lsb) 4.0 1196/98 g09 1.0 2.0 3.0 5.0 0.5 1.5 2.5 3.5 4.5 t a = 25c v cc = 5v f clk = 12mhz 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 supply voltage (v) 2.5 magnitude of gain error (lsb) 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 3.5 4.5 5.0 1196/98 g10 3.0 4.0 5.5 6.0 t a = 25c f clk = 3mhz v ref = v cc supply voltage (v) 2.5 19 17 15 13 11 9 7 5 4.0 5.0 1196/98 g11 3.0 3.5 4.5 5.5 6.0 maximum clock frequency (mhz) t a = 25c v ref = v cc source resistance () clock frequency (mhz) 18 16 14 12 10 8 6 4 2 0 1 100 1k 100k 1196/98 g12 10 10k t a = 25c v cc = v ref = 5v r source C v in +in Cin temperature (c) C55 minimum clock frequency (khz) 100 90 80 70 60 50 40 30 20 10 0 C15 25 45 125 1196/98 g13 C35 5 65 85 105 v cc = 5v v ref = 5v supply voltage (v) 2.5 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4.0 5.0 1196/98 g14 3.0 3.5 4.5 5.5 6.0 peak-to-peak adc noise (lsb) t a = 25c v ref = v cc source resistance () 1 100 s&h acquisition time (ns) 1000 10000 100 10k 1196/98 g15 10 1k t a = 25c v cc = v ref = 5v r source + v in +in Cin *as the frequency is decreased from 12mhz, minimum clock frequency ( error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 12mhz value is first detected.
ltc1196/ltc1198 9 119698fb typical performance characteristics differential nonlinearity vs code at 2.7v effective bits and s/(n + d) vs input frequency digital input logic threshold vs supply voltage d out delay time vs supply voltage d out delay time vs temperature input channel leakage current vs temperature integral nonlinearity vs code at 5v differential nonlinearity vs code at 5v supply voltage (v) 2.5 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 4.0 5.0 1196/98 g16 3.0 3.5 4.5 5.5 6.0 logic threshold (v) t a = 25c supply voltage (v) 2.5 140 120 100 80 60 40 20 0 4.0 5.0 1196/98 g17 3.0 3.5 4.5 5.5 6.0 d out delay time, t ddo (ns) t a = 25c v ref = v cc temperature (c) C60 d out delay time, t ddo (ns) 160 140 120 100 80 60 40 20 0 100 1196/98 g18 C20 20 60 140 C40 0 40 80 120 v cc = 5v v ref = v cc v cc = 2.7v integral nonlinearity vs code at 2.7v temperature (c) C60 leakage current (na) 1000 100 10 1 0.1 0.01 100 1196/98 g19 C20 20 60 140 C40 0 40 80 120 v cc = 5v v ref = 5v on channel off channel code 0 integral nonlinearity error (lsb) 0.5 64 128 160 1196/98 g20 32 96 192 224 256 0 C0.5 v cc = 5v v ref = 5v f clk = 12mhz code 0 differential nonlinearity error (lsb) 0.5 64 128 160 1196/98 g21 32 96 192 224 256 0 C0.5 v cc = 5v v ref = 5v f clk = 12mhz code 0 integral nonlinearity error (lsb) 0.5 64 128 160 1196/98 g22 32 96 192 224 256 0 C0.5 v cc = 2.7v v ref = 2.5v f clk = 3mhz code 0 differential nonlinearity error (lsb) 0.5 64 128 160 1196/98 g23 32 96 192 224 256 0 C0.5 v cc = 2.7v v ref = 2.5v f clk = 3mhz input frequency (hz) 1k s/(n + d) (db) 8 7 6 5 4 3 2 1 0 10k 100k 1m 1196/98 g24 50 44 effective number of bits (enobs) v ref =v cc = 2.7v f smpl = 383khz (ltc1196) f smpl = 287khz (ltc1198) v ref =v cc = 5v f smpl = 1mhz (ltc1196) f smpl = 750khz (ltc1198) t a = 25c
ltc1196/ltc1198 10 119698fb typical performance characteristics 4096 point fft plot at 5v fft output of 455khz am signal digitized at 1msps 4096 point fft plot at 2.7v frequency (khz) 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 400 1196/98 g25 100 200 300 500 v cc = 5v f in = 29khz f smpl = 882khz magnitude (db) frequency (khz) 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 150 1196/98 g26 50 100 200 v cc = 2.7v f in = 29khz f smpl = 340khz magnitude (db) frequency (khz) 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 400 1196/98 g27 100 200 300 500 v cc = 5v f in = 455khz with 20khz am f smpl = 1mhz magnitude (db) power supply feedthrough vs ripple frequency power supply feedthrough vs ripple frequency s/(n + d) vs reference voltage and input frequency ripple frequency (hz) 1k 0 C10 C20 C30 C40 C50 C60 C70 10k 100k 1m 1196/98 g28 feedthrough (db) t a = 25c v cc (v ripple = 20mv) f clk = 12mhz ripple frequency (hz) 1k 0 C10 C20 C30 C40 C50 C60 C70 10k 100k 1m 1196/98 g29 feedthrough (db) t a = 25c v cc (v ripple = 10mv) f clk = 5mhz reference voltage (v) 1.25 signal to noise plus distortion (db) 50 45 40 35 30 25 2.75 3.75 5.25 1196/98 g30 - 1.75 2.25 3.25 4.25 4.75 v cc = 5v f in = 500khz f in = 200khz f in = 100khz intermodulation distortion at 2.7v intermodulation distortion at 5v s/(n + d) vs input level frequency (khz) 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 200 1196/98 g31 50 100 150 250 v cc = 2.7v f1 = 100khz f2 = 110khz f smpl = 420khz magnitude (db) frequency (khz) 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 300 1196/98 g32 100 200 400 v cc = 5v f1 = 200khz f2 = 210khz f smpl = 750khz magnitude (db) input level (db) C40 signal to noise-plus-distortion (db) 50 40 30 20 10 0 C25 C15 0 1196/98 g33 C35 C30 C20 C10 C5 v ref = v cc = 5v f in = 500khz f smpl = 1mhz
ltc1196/ltc1198 11 119698fb typical performance characteristics spurious-free dynamic range vs frequency output amplitude vs input frequency input frequency (hz) 1k peak-to-peak output (%) 10m 1196/98 g34 10k 100k 1m 100 80 60 40 20 0 v ref = v cc = 2.7v v ref = v cc = 5v frequency (hz) 1k 70 60 50 40 30 20 10 0 1m 1196/98 g35 10k 100k 10m spurious-free dynamic range (db) t a = 25c v cc = 3v f clk = 5mhz v cc = 5v f clk = 12mhz pin functions ltc1196 cs (pin 1): chip select input. a logic low on this input enables the ltc1196. a logic high on this input disables the ltc1196. in + (pin 2): analog input. this input must be free of noise with respect to gnd. in C (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. v ref (pin 5): reference input. the reference input de? nes the span of the a/d converter and must be kept free of noise with respect to gnd. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the se- rial data transfer. v cc (pin 8): power supply voltage. this pin provides power to the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane. ltc1198 cs /shutdown (pin 1): chip select input. a logic low on this input enables the ltc1198. a logic high on this input disables the ltc1198 and disconnects the power to the ltc1198. cho (pin 2): analog input. this input must be free of noise with respect to gnd. ch1 (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. d in (pin 5): digital data input. the multiplexer address is shifted into this input. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the se- rial data transfer. v cc (v ref ) (pin 8): power supply and reference volt- age. this pin provides power and de? nes the span of the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane.
ltc1196/ltc1198 12 119698fb block diagram C + c smpl bias and shutdown circuit serial port v cc (v cc /v ref ) clk d out in + (ch0) in C (ch1) high speed comparator capacitive dac sar v ref (d in ) gnd pin names in parentheses refer to the ltc1198 cs ( cs /shutdown) 1196/98 bd test circuits on and off channel leakage current 5v a a i off i on polarity off channel on channel 1196/98 tc01 ? ? ? ? load circuit for t ddo , t r and t f d out 1.4v 3k 100pf test point 1196/98 tc02 voltage waveform for d out rise and fall times, t r , t f voltage waveform for d out delay time, t ddo , t hdo d out v ol v oh t r t f 1196/98 tc04 clk d out t ddo 1196/98 tc03 v ih t hdo v oh v ol
ltc1196/ltc1198 13 119698fb test circuits load circuit for t dis and t en voltage waveforms for t dis d out 3k 20pf test point v cc t dis waveform 2, t en t dis waveform 1 1196/98 tc05 d out waveform 1 (see note 1) v ih t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. 1196/98 tc06 voltage waveforms for t en 1196/98 tc07 cs ltc1196 1 clk d out t en b7 v ol 23 4 voltage waveforms for t en 1234 5 ltc1198 d in clk start d out t en b7 v ol 1196/98 tc08 cs 67
ltc1196/ltc1198 14 119698fb applications information overview the ltc1196/ltc1198 are 600ns sampling 8-bit a/d con- verters packaged in tiny 8-pin so packages and operating on 3v to 6v supplies. the adcs draw only 10mw from a 3v supply or 50mw from a 5v supply. both the ltc1196 and the ltc1198 contain an 8-bit, switched-capacitor adc, a sample-and-hold, and a serial port (see the block diagram). the on-chip sample-and- holds have full-accuracy input bandwidths of 1mhz. although they share the same basic design, the ltc1196 and ltc1198 differ in some respects. the ltc1196 has a differential input and has an external reference input pin. it can measure signals ? oating on a dc common mode voltage and can operate with reduced spans below 1v. the ltc1198 has a 2-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. it also automatically powers down when not performing conversion, drawing only leakage current. serial interface the ltc1196/ltc1198 will interface via three or four wires to asics, plds, microprocessors, dsps, or shift registers (see operating sequence in figures 1 and 2). to run at their fastest conversion rates (600ns), they must be clocked at 14.4mhz. hc logic families and any high speed asic or pld will easily interface to the adcs at that speed (see data transfer and typical application sections). full speed operation from a 3v supply can still be achieved with 3v asics, plds or hc logic circuits. cs b1 b2 b3 b4 b5 b6 b7 t su cs t ddo null bits hi-z d out 1196/98 f01 hi-z *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely b0* null bits b0 t cyc (12 clks) t cyc (8.5 clks) t smpl t smpl 1196/98 f02 power down sgl/ diff dummy b3 b4 b5 b6 b7 null bits hi-z hi-z start odd/ sign dont care b0* b2 b1 *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely dummy t ddo clk d in d out cs t su cs t cyc (16 clks) t conv (8.5 clks) t smpl (2.5 clks) figure 2. ltc1198 operating sequence example: differential inputs (ch1, ch0) figure 1. ltc1196 operating sequence
ltc1196/ltc1198 15 119698fb applications information connection to a microprocessor or a dsp serial port is quite simple (see the data transfer section). it requires no additional hardware, but the speed will be limited by the clock rate of the microprocessor or the dsp which limits the conversion time of the ltc1196/ltc1198. data transfer data transfer differs slightly between the ltc1196 and the ltc1198. the ltc1196 interfaces over three lines: cs , clk and d out . a falling cs initiates data transfer as depicted by the ltc1196 operating sequence in figure 1. after cs falls, the ? rst clk pulse enables d out . after two null bits, the a/d conversion result is output on the d out line. bringing cs high resets the ltc1196 for the next data exchange. the ltc1198 can transfer data with three or four wires. the additional input, d in , is used to select the 2-channel mux con? guration. the data transfer between the ltc1198 and the digital systems can be broken into two sections: input data word and a/d conversion result. first, each bit of the input data word is captured on the rising clk edge by the ltc1198. second, each bit of the a/d conversion result on the d out line is updated on the rising clk edge by the ltc1198. this bit should be captured on the next rising clk edge by the digital systems (see the a/d conversion result section). data transfer is initiated by a falling chip select ( cs ) signal as depicted by the ltc1198 operating sequence in figure 2. after cs falls, the ltc1198 looks for a start bit. after the start bit is received, the 4-bit input word is shifted into the d in input. the ? rst two bits of the input word con? gure the ltc1198. the last two bits of the input word allow the adc to acquire the input voltage by 2.5 clocks before the conversion starts. after the conversion starts, two null bits and the conversion result are output on the d out line. at the end of the data exchange cs should be brought high. this resets the ltc1198 in preparation for the next data exchange. input data word the ltc1196 requires no d in word. it is permanently con- ? gured to have a single differential input. the conversion result is output on the d out line in an msb-? rst sequence, followed by zeros inde? nitely if clocks are continuously applied with cs low. the ltc1198 clocks data into the d in input on the ris- ing edge of the clock. the input data word is de? ned as follows: d in1 d in2 d out1 d out2 cs shift mux address in 2 null bits shift a/d conversion result out 1196/98 ai01 sgl/ diff odd/ sign dummy start mux address dummy bits 119698 ai02 dummy start bit the ? rst logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer. the ltc1198 will ignore all leading zeros which precede this logical one . after the start bit is received, the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. multiplexer (mux) address the two bits of the input word following the start bit as- sign the mux con? guration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following table. in single-ended mode, all input channels are measured with respect to gnd. mux address sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + C 1 + C + gnd C C single-ended mux mode differential mux mode 1196/98 ai03 ltc1198 channel selection
ltc1196/ltc1198 16 119698fb applications information dummy bits the last two bits of the input word following the mux ad- dress are dummy bits. either bit can be a logical one or a logical zero . these two bits allow the adc 2.5 clocks to acquire the input signal after the channel selection. a/d conversion result both the ltc1196 and the ltc1198 have the a/d conver- sion result appear on the d out line after two null bits (see the operating sequences in figures 1 and 2). data on the d out line is updated on the rising edge of the clk line. the d out data should also be captured on the rising clk edge by the digital systems. data on the d out line remains valid for a minimum time of t hdo (30ns at 5v) to allow the capture to occur (see figure 3). unipolar transfer curve the ltc1196/ltc1198 are permanently con? gured for unipolar only. the input span and code assignment for this conversion type are shown in the following ? gures. clk v ih t ddo d out 1196/98 tc03 v oh v ol t hdo figure 3. voltage waveform for d out delay time, t ddo and t hdo unipolar transfer curve 0v 1lsb v ref C 2lsb v ref C 1lsb v ref v in 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 1196/98 ai04 unipolar output code output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 input voltage v ref C 1lsb v ref C 2lsb ? ? ? 1lsb 0v input voltage (v ref = 5.000v) 4.9805v 4.9609v ? ? ? 0.0195v 0v 1196/98 ai05 1 2 3 4 clk data (d in /d out ) start sgl/ diff odd/sign dummy bits latched by ltc1198 ltc1198 controls data line and sends a/d result back to the digital system the digital system controls data line and sends mux address to ltc1198 the digital system must release data line after 5th rising clk and before the 5th falling clk ltc1198 takes control of data line on 5th falling clk cs 1196/98 f04 5 dummy figure 4. ltc1198 operation with d in and d out tied together operation with d in and d out tied together the ltc1198 can be operated with d in and d out tied together. this eliminates one of the lines required to com- municate to the digital systems. data is transmitted in both directions on a single wire. the pin of the digital systems connected to this data line should be con? gurable as either an input or an output. the ltc1198 will take control of the data line and drive it low on the ? fth falling clk edge after the start bit is received (see figure 4). therefore, the port line of the digital systems must be switched to an input before this happens to avoid a con? ict.
ltc1196/ltc1198 17 119698fb applications information reducing power consumption the ltc1196/ltc1198 can sample at up to a 1mhz rate, drawing only 50mw from a 5v supply. power consumption can be reduced in two ways. using a 3v supply lowers the power consumption on both devices by a factor of ? ve, to 10mw. the ltc1198 can reduce power even further because it shuts down whenever it is not converting. figure 5 shows the supply current versus sample rate for the ltc1196 and ltc1198 on 3v and 5v. to achieve such a low power consumption, especially for the ltc1198, several things must be taken into consideration. d in and clk with cs = high; they can continue to run without drawing current. minimize cs low time (ltc1198) in systems that have signi? cant time between conver- sions, lowest power drain will occur with the minimum cs low time. bringing cs low, transferring data as quickly as possible, then bringing it back high will result in the lowest current drain. this minimizes the amount of time the device draws power. operating on other than 5v supplies the ltc1196/ltc1198 operate from single 2.7v to 6v supplies. to operate the ltc1196/ltc1198 on other than 5v supplies, a few things must be kept in mind. input logic levels the input logic levels of cs , clk and d in are made to meet ttl on 5v supply. when the supply voltage varies, the input logic levels also change (see the digital input logic threshold vs supply voltage curve in the typical performance characteristics section). for these two adcs to sample and convert correctly, the digital inputs have to be in the logical low and high relative to the operating supply voltage. if achieving micropower consumption is desirable on the ltc1198, the digital inputs must go rail-to-rail between supply voltage and ground (see the reducing power consumption section). clock frequency the maximum recommended clock frequency is 14.4mhz at 25c for the ltc1196/ltc1198 running off a 5v supply. with the supply voltage changing, the maximum clock frequency for the devices also changes (see the maximum clock rate vs supply voltage curve in the typical perfor- mance characteristics section). if the supply is reduced, the clock rate must also be reduced. at 3v, the devices are speci? ed with a 5.4mhz clock at 25c. sample rate (hz) 0.01 supply current (ma) 0.1 1 10 100 10k 100k 1196/98 f05 0.001 1k 1m lt1198 v cc = 2.87v lt1196 v cc = 2.87v lt1198 v cc = 5v lt1198 v cc = 5v figure 5. supply current vs sample rate for ltc1196/ltc1198 operating on 5v and 2.7v supplies shutdown (ltc1198) figure 2 shows the operating sequence of the ltc1198. the converter draws power when the cs pin is low and powers itself down when that pin is high. for lowest power consumption in shutdown, the cs pin should be driven with cmos levels (0v to v cc ) so that the cs input buffer of the converter will not draw current. when the cs pin is high (= supply voltage), the ltc1198 is in shutdown mode and draws only leakage current. the status of the d in and clk input has no effect on the supply current during this time. there is no need to stop
ltc1196/ltc1198 18 119698fb applications information mixed supplies it is possible to have a digital system running off a 5v supply and communicate with the ltc1196/ltc1198 operating on a 3v supply. achieving this reduces the outputs of d out from the adcs to toggle the equivalent input of the digital system. the cs , clk and d in inputs of the adcs will take 5v signals from the digital system without causing any problem (see the digital input logic threshold vs supply voltage curve in the typical performance characteristics section). with the ltc1196 operating on a 3v supply, the output of d out only goes between 0v and 3v. this signal easily meets ttl levels (see figure 6). board layout considerations grounding and bypassing the ltc1196/ltc1198 are easy to use if some care is taken. they should be used with an analog ground plane and single-point grounding techniques. the gnd pin should be tied directly to the ground plane. the v cc pin should be bypassed to the ground plane with a 1f tantalum with leads as short as possible. if the power supply is clean, the ltc1196/ltc1198 can also operate with smaller 0.1f surface mount or ceramic bypass ca- pacitors. all analog inputs should be referenced directly to the single-point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. sample-and-hold both the ltc1196 and the ltc1198 provide a built-in sample-and-hold (s&h) function to acquire the input signal. the s&h acquires the input signal from + input during t smpl as shown in figures 1 and 2. the s&h of the ltc1198 can sample input signals in either single-ended or differential mode (see figure 7). 3v 4.7f mpu (e.g., 8051) 5v p1.4 p1.3 p1.2 1196/98 f06 differential inputs common mode range 0v to 3v 3v v cc clk d out v ref ltc1196 Cin gnd +in cs figure 6. interfacing a 3v powered ltc1196 to a 5v system clk d in d out + input C input d l o h e l p m a s + input must settle during this time t smpl t conv cs start sgl/ diff dummy 1st bit test: C input must settle during this time b7 1196/98 f07 odd/sign dummy dont care figure 7. ltc1198 + and C input settling windows
ltc1196/ltc1198 19 119698fb applications information single-ended inputs the sample-and-hold of the ltc1198 allows conversion of rapidly varying signals. the input voltage is sampled during the t smpl time as shown in figure 7. the sampling interval begins as the bit preceding the ? rst dummy bit is shifted in and continues until the falling clk edge after the second dummy bit is received. on this falling edge, the s&h goes into hold mode and the conversion begins. differential inputs with differential inputs, the adc no longer converts just a single voltage but rather the difference between two volt- ages. in this case, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the voltage on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be performed accurately. the conversion time is 8.5 clk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input, this error would be: v error(max) = v peak ? 2 ? ? f(C) ? 8.5/fclk where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. v error is proportional to f(C) and inversely proportional to f clk . for a 60hz signal on the C input to generate a 1/4lsb error (5mv) with the converter running at clk = 12mhz, its peak value would have to be 18.7v. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1196/ltc1198 have one capacitive switching input current spike per conversion. these current spikes settle quickly and do not cause a problem. however, if source resistances larger than 100 are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. + input settling the input capacitor of the ltc1196 is switched onto + input at the end of the conversion and samples the input signal until the conversion begins (see figure 1). the input capacitor of the ltc1198 is switched onto + input during the sample phase (t smpl , see figure 7). the sample phase is 2.5 clk cycles before conversion starts. the voltage on the + input must settle completely within t smpl for the ltc1196/ltc1198. minimizing r source + will improve the input settling time. if a large + input source resistance must be used, the sample time can be increased by allowing more time between conversions for the ltc1196 or by using a slower clk frequency for the ltc1198. C input settling at the end of the t smpl , the input capacitor switches to the C input and conversion starts (see figures 1 and 7). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage settle completely during the ? rst clk cycle of the conversion time and be free of noise. minimizing r source C will improve settling time. if a large C input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. input op amps when driving the analog inputs with an op amp it is im- portant that the op amp settle within the allowed time (see figures 1 and 7). again, the + and C input sampling times can be extended as described above to accommodate slower op amps. to achieve the full sampling rate, the analog input should be driven with a low impedance source (<100) or a high speed op amp (e.g., the lt1223, lt1191 or lt1226). higher impedance sources or slower op amps can easily be accommodated by allowing more time for the analog input to settle as described above.
ltc1196/ltc1198 20 119698fb applications information source resistance the analog inputs of the ltc1196/ltc1198 look like a 25pf capacitor (c in ) in series with a 120 resistor (r on ) as shown in figure 8. c in gets switched between the selected + and C inputs once during each con- version cycle. large external source resistors will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within t smpl . reference input the voltage on the reference input of the ltc1196 de? nes the voltage span of the a/d converter. the reference input has transient capacitive switching currents which are due to the switched-capacitor conversion technique (see figure 9). during each bit test of the conversion (every clk cycle), a capacitive current spike will be generated on the reference pin by the adc. these high frequency current spikes will settle quickly and do not cause a problem if the reference input is bypassed with at least a 0.1f capacitor. the reference input can be driven with standard volt- age references. bypassing the reference with a 0.1f capacitor is recommended to keep the high frequency impedance low as described above. some references require a small resistor in series with the bypass capaci- tor for frequency stability. see the individual reference data sheet for details. reduced reference operation the minimum reference voltage of the ltc1198 is limited to 2.7v because the v cc supply and reference are internally tied together. however, the ltc1196 can operate with reference voltages below 1v. the effective resolution of the ltc1196 can be increased by reducing the input span of the converter. the ltc1196 exhibits good linearity and gain over a wide range of reference voltages (see the linearity and full-scale error vs reference voltage curves in the typical performance characteristics section). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy require- ment placed on the converter. the following factors must be considered when operating at low v ref values. 1. offset 2. noise offset with reduced v ref the offset of the ltc1196 has a larger effect on the output code when the adc is operated with reduced reference voltage. the offset (which is typically a ? xed voltage) be- comes a larger fraction of an lsb as the size of the lsb is reduced. the unadjusted offset error vs reference voltage curve in the typical performance characteristics section depicts how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 2mv which is 0.1lsb with a 5v reference becomes 0.5lsb with a 1v reference and 2.5lsb with a 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input of the ltc1196. r on 120 c in 25pf ltc1196 ltc1198 + input v in + C input r source C r source + v in C 1196/98 f08 l t smpl t smpl n figure 8. analog input equivalent circuit r on 5pf to 30pf ltc1196 ref + r out v ref every clk cycle 5 4 gnd 1196/98 f09 figure 9. reference input equivalent circuit
ltc1196/ltc1198 21 119698fb applications information noise with reduced v ref the total input referred noise of the ltc1196 can be reduced to approximately 2mv p-p using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insigni? cant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. for operation with a 5v reference, the 2mv noise is only 0.1lsb peak-to-peak. in this case, the ltc1196 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a signi? cant fraction of an lsb and cause undesirable jit- ter in the output code. for example, with a 1v reference, this same 2mv noise is 0.5lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 1lsb. if the reference is further reduced to 200mv, the 2mv noise becomes equal to 2.5lsb and a stable code is dif? cult to achieve. in this case averaging readings is necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. dynamic performance the ltc1196/ltc1198 have exceptionally high speed sampling capability. fast fourier transform (fft) test techniques are used to characterize the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using a fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 10 shows a typical ltc1196 fft plot. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the adcs output. the output is band limited to frequencies above dc and below one half the sampling frequency. figure 10 shows a typical spectral content with a 882khz sampling rate. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to s/(n + d) by the equation: n = [s/(n + d) C1.76]/6.02 frequency (khz) 0 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 400 1196/98 g25 100 200 300 500 v cc = 5v f in = 29khz f smpl = 882khz magnitude (db) figure 10. ltc1196 nonaveraged, 4096 point fft plot
ltc1196/ltc1198 22 119698fb applications information where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 1.2mhz with a 5v supply the ltc1196 maintains above 7.5 enobs at 400khz input frequency. above 500khz the enobs gradually decline, as shown in figure 11, due to increasing second harmonic distortion. the noise ? oor remains low. figure 11. effective bits and s/(n + d) vs input frequency total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half of the sampling frequency. thd is de? ned as: thd = ++++ 20log vvv v v 2 2 3 2 4 2 n 2 1 ... where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through the nth harmonics. the typical thd speci? cation in the dynamic accuracy table (see the electrical charac- teristics section) includes the 2nd through 5th harmonics. with a 100khz input signal, the ltc1196/ltc1198 have typical thd of 50db and 49db with v cc = 5v and v cc = 3v, respectively. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a + f b ) and (f a C f b ) while 3rd order imd terms include (2f a + f b ), (2f a C f b ), (f a + 2f b ) and (f a C 2f b ). if the two input sine waves are equal in magnitudes, the value (in db) of the 2nd order imd products can be expressed by the follow- ing formula: imd f f mplitude f f ab ab () = () 20log a amplitude?a t t?f a ? ? ? ? ? ? ? ? for input frequencies of 499khz and 502khz, the imd of the ltc1196/ltc1198 is 51db with a 5v supply. peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in dbs relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input. the full-linear bandwidth is the input frequency at which the effective bits rating of the adc falls to 7 bits. beyond this frequency, distortion of the sampled input signal increases. the ltc1196/ltc1198 have been designed to optimize input bandwidth, allowing the adcs to unders- ample input signals with frequencies above the converters nyquist frequency. input frequency (hz) 1k s/(n + d) (db) 8 7 6 5 4 3 2 1 0 10k 100k 1m 11968 f11 50 44 effective number of bits (enobs) v ref =v cc = 2.7v f smpl = 383khz (ltc1196) f smpl = 287khz (ltc1198) v ref =v cc = 5v f smpl = 1mhz (ltc1196) f smpl = 750khz (ltc1198) t a = 25c
ltc1196/ltc1198 23 119698fb applications information 3v versus 5v performance comparison table 1 shows the performance comparison between 3v and 5v supplies. the power dissipation drops by a factor of ? ve when the supply is reduced to 3v. the converter slows down somewhat but still gives excellent performance on a 3v rail. with a 3v supply, the ltc1196 converts in 1.6s, samples at 450khz, and provides a 500khz linear- input bandwidth. dynamic accuracy is excellent on both 5v and 3v. the adcs typically provide 49.3db of 7.9 enobs of dynamic accuracy at both 3v and 5v. the noise ? oor is extremely low, corresponding to a transition noise of less than 0.1lsb. dc accuracy includes 0.5lsb total unadjusted error at 5v. at 3v, linearity error is 0.5lsb while total unadjusted error increases to 1lsb. table 1. 5v/3v performance comparison ltc1196-1 5v 3v p diss 50mw 10mw max f smpl 1mhz 383khz min t conv 600ns 1.6s inl (max) 0.5lsb 0.5lsb typical enobs 7.9 at 300khz 7.9 at 100khz linear input bandwidth (enobs > 7) 1mhz 500khz ltc1198-1 p diss 50mw 10mw p diss (shutdown) 15w 9w max f smpl 750khz 287khz min t conv 600ns 1.6s inl (max) 0.5lsb 0.5lsb typical enobs 7.9 at 300khz 7.9 at 100khz linear input bandwidth (enobs > 7) 1mhz 500khz typical applications pld interface using the altera epm5064 the altera epm5064 has been chosen to demonstrate the interface between the ltc1196 and a pld. the epm5064 is programmed to be a 12-bit counter and an equivalent 74hc595 8-bit shift register, as shown in figure 12. the circuit works as follows: bringing ena high makes the cs output high and the en input low to reset the ltc1196 and disable the shift register. bringing ena low, the cs output goes high for one clk cycle with every 12 clk cycles. the inverted signal, en, of the cs output makes the 8-bit data available on the b0-b7 lines. figures 13 and 14 show the interconnection between the ltc1196 and epm5064 and the timing diagram of the signals between these two devices. the clk frequency in this circuit can run up to f clk(max) of the ltc1196. 1196/98 f12 data clk 12-bit converter cs ena en clk b0-b7 8-bit shift register cs ena clk data b0-b7 3, 14, 25, 36 epm5064 clk 33 23 34 35 1196/98 f13 v cc + C data 1 37 38 39 40 41 42 44 9-13, 21, 31, 32, 43 clk b7 b0 ena Cin gnd v cc clk d out +in cs 1 2 3 4 8 7 6 5 ltc1196 v ref 1f reserve pins of epm5064: 2, 4-8,15-20, 22, 24, 26-30 figure 12. an equivalent circuit of the epm5064 figure 13. interfacing the ltc1196 to the altera emp5064 pld
ltc1196/ltc1198 24 119698fb typical applications interfacing the ltc1198 to the tms320c25 dsp figure 15 illustrates the interface between the ltc1198 8-bit data acquisition system and the tms320c25 digital signal processor (dsp). the interface, which is optimized for speed of transfer and minimum processor supervision, can complete a conversion and shift the data in 4s with f clk = 5mhz. the cycle time, 4s, of each conversion is limited by maximum clock frequency of the serial port of the tms320c25 which is 5mhz. the supply voltage for the ltc1198 in figure 15 can be 2.7v to 6v with f clk = 5mhz. at 2.7v, f clk = 5mhz will work at 25c. see the recommended operating conditions table in the electrical characteristics section for limits over temperature. hardware description the circuit works as follows: the ltc1198 clock line controls the a/d conversion rate and the data shift rate. data is transferred in a synchronous format over d in and d out . the serial port of the tms320c25 is compatible with that of the ltc1198. the data shift clock lines (clkr, clkx) are inputs only. the data shift clock comes from an external source. inverting the shift clock is necessary because the ltc1198 and the tms320c25 clock the input data on opposite edges. the schematic of figure 15 is fed by an external clock source. the signal is fed into the clk pin of the ltc1198 directly. the signal is inverted with a 74hc04 and then applied to the data shift clock lines (clkr, clkx). the framing pulse of the tms320c25 is fed directly to the cs of the ltc1198. dx and dr are tied directly to d in and d out , respectively. 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 data clk cs b7 b4 b6 b5 b3 b1 b2 b0 time (ns) 1196/98 f14 figure 14. the timing diagram 1196/98 f15 5mhz clk clkx clkr fsr fsx dx dr clk ltc1198 tms320c25 cs d in d out ch0 ch1 figure 15. interfacing the ltc1198 to the tms320c25 dsp
ltc1196/ltc1198 25 119698fb typical applications the timing diagram of figure 16 was obtained from the circuit of figure 15. the clk was 5mhz for the timing diagram and the tms320c25 clock rate was 40mhz. figure 17 shows the timing diagram with the ltc1198 running off a 2.7v supply and 5mhz clk. software description the software con? gures and controls the serial port of the tms320c25. the code ? rst sets up the interrupt and reset vectors. on reset the tms320c25 starts executing code at the label init. upon completion of a 16-bit data transfer, an inter- rupt is generated and the dsp will begin executing code at the label rint. in the beginning, the code initializes registers in the tms320c25 that will be used in the transfer routine. the interrupts are temporarily disabled. the data memory page pointer register is set to zero. the auxiliary register pointer is loaded with one and auxiliary register one is loaded with the value 200 hexadecimal. this is the data memory loca- tion where the data from the ltc1198 will be stored. the interrupt mask register (imr) is con? gured to recognize the rint interrupt, which is generated after receiving the last of 16 bits on the serial port. this interrupt is still dis- abled at this time. the transmit framing synchronization pin (fsx) is con? gured to be an output. the f0 bit of the status register st1, is initialized to zero which sets up the serial port to operate in the 16-bit mode. next, the code in txrx routine starts to transmit and receive data. the din word is loaded into the acc and shifted left eight times so that it appears as in figure 18. this d in word con? gures the ltc1198 for ch0 with respect to ch1. the d in word is then put in the transmit register and the rint interrupt is enabled. the nop is repeated 3 times to mask out the interrupts and minimize the cycle time of the conversion to be 20 clock cycles. all clocking and cs functions are performed by the hardware. cs clk d in vertical: 5v/div d out null bits msb (b7) horizontal: 1500ns/div lsb (b0) 1196/98 f16 figure 16. scope trace the ltc1198 running off 5v supply in the circuit of figure 15 cs clk d in vertical: 5v/div d out null bits msb (b7) horizontal: 500ns/div lsb (b0) 1196/98 f17 figure 17. scope trace the ltc1198 running off 1.7v supply in the circuit of figure 15 l1196/98 f18 b15 b8 0 1 start 0 s/ d 0 o/s 0 dummy 1 dummy 0 0 figure 18. d in word in acc of tms20c25 for the circuit in figure 15
ltc1196/ltc1198 26 119698fb typical applications once rint is generated the code begins execution at the label rint. this code stores the d out word from the ltc1198 in the acc and then stores it in location 200 hex. the data appears in location 200 hex right-justi? ed as shown in figure 19. the code is set up to continually loop, so at this point the code jumps to label txrx and repeats from here. l1196/98 f19 msb lsb x x x x x x x x 7 6 5 4 3 2 1 0 d out from ltc1198 stored in tms320c25 ram > 200 figure 19. memory map for the circuit in figure 15 label mnemonic comments aorg b 0 init on reset code execution starts at 0 branch to initialization routine aorg b >26 rint address to rint interrupt vector branch to rint service routine init aorg dint ldpk larp lrlk lack sacl stxm fort >32 >0 >1 ar1, >200 >10 >4 0 main program starts here disable interrupts set data memory page pointer to 0 set auxiliary register pointer to 1 set auxiliary register 1 to >200 load imr config word into acc store imr config word into imr configure fsx as an output set serial port to 16-bit mode txrx lack sfsm rptk sfl sacl eint >44 7 >1 load ltc1198 d in word into acc fsx pulses generated on xsr load repeat next instruction 8 times shifts d in word to right position put d in word in transmit register enable interrupt (disable on rint) rptk nop 2 minimize the conversion cycle time to be 20 clock cycles rint zals sacl b end >0 *, 0 txrx store ltc1198 d out word in acc store acc in location >200 branch to transmit receive routine figure 20. tms320c25 code for the circuit in figure 15
ltc1196/ltc1198 27 119698fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc1196/ltc1198 28 119698fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1993 lt 0609 rev b ? printed in usa related parts part number description comments adcs ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.5v span ltc1403/ltc1403a 12-/14-bit, 2.8msps serial adcs 3v, 15mw, unipolar inputs, msop package ltc1403-1/ltc1403a-1 12-/14-bit, 2.8msps serial adcs 3v, 15mw, bipolar inputs, msop package ltc1405 12-bit, 5msps parallel adc 5v, selectable spans, 115mw ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adcs 3v, 2-channel differential, unipolar inputs, 14mw, msop package ltc1407-1/ltc1407a-1 12-/14-bit, 3msps simultaneous sampling adcs 3v, 2-channel differential, bipolar inputs, 14mw, msop package ltc1411 14-bit, 2.5msps parallel adc 5v, selectable spans, 80db sinad ltc1412 12-bit, 3msps parallel adc 5v supply, 2.5v span, 72db sinad lct1414 14-bit, 2.2msps parallel adc 5v supply, 2.5v span, 78db sinad ltc1420 12-bit, 10msps parallel adc 5v, selectable spans, 72db sinad ltc1604 16-bit, 333ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1608 16-bit, 500ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1609 16-bit, 250ksps serial adc 5v, con? gurable bipolar/unipolar inputs ltc1864/ltc1865 16-bit, 250ksps serial adcs 5v supply, 1 and 2 channel, 4.3mw, msop package ltc2355-12/ ltc2355-14 12-bit, 3.5msps serial adcs 3.3v supply, 0v to 2.5v span, msop package ltc2356-12/ltc2356-14 12-/14-bit, 3.5msps serial adcs 3.3v supply, 1.25v span, msop package dacs ltc1666/ltc1667/ltc1668 12-/14-/16-bit, 50msps dacs 87db sfdr, 20ns settling time ltc1592 16-bit, serial softspan? i out dac 1lsb inl/dnl, software selectable spans references lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.04% initial accuracy, 3ppm drift lt1460-2.5 micropower series voltage reference 0.1% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation.

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